Conditional cosimulation #51
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Description & Motivation
Sometimes it is desirable to be able to have multiple implementations of a module, one with ROHD and one with SystemVerilog, and reuse the same testbench for both. Currently, you need to point to
ExternalSystemVerilogModule, which is a base type, which makes it annoying and inconvenient for that type of testbench setup.This PR introduces an ability to conditionally enable cosim on a module, as well as point to any
Modulewith aSystemVerilogmixin applied.Related Issue(s)
Fix #43
Testing
TODO: need to add more testing for this
Backwards-compatibility
No
Documentation
TODO: Yes, we should include some examples and documentation for this approach.