Skip to content
Merged
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Original file line number Diff line number Diff line change
Expand Up @@ -52,3 +52,43 @@ Registers
* The same 10 inputs discussed above
* An additional 3 inputs specifying which register the output should be saved to



New Operation
=============

Currently there is no way to actually load data into the system.

#. Add a new mode/instruction such that data can be loaded into a specific register

* Currently 1 bit is used to specify ALU or comparator operations

* These can be thought of as *modes*


* Add an additional bit to allow for selecting between up to 4 modes

* 2 mode bits
* 3 bits that served as selecting a specific operation
* Two sets of 3 bits for specifying 2 source registers
* 3 bits for a destination register


* Update the system such that one of these 4 modes allows for loading data directly to a register

* The 3 destination register bits specify where the data is to be stored
* 8 bits of the 9 available for the operator and 3 source registers specify the 8 bit data


* For example, consider the below bit patterns and their meanings

* ``00 110 101 010 111`` --- ``add`` on registers 5 and 2 and store in 7
* ``01 110 101 010 111`` --- ``>=`` on registers 5 and 2 and store in 7
* ``10 1 10101010 111`` --- Store ``0b10101010`` (``170``) in register 7



#. Add a new forth mode such that data can be copy between registers

* Here, only one set of 3 bits specifying the source register is required
* ``11 110 101 010 111`` --- Copy contests of register 2 to register 7