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@jameshughes89 jameshughes89 commented Mar 24, 2025

What

  1. Enhance the ESAP system design to include boolean operators and include them as instructions
  2. Add RAM to the lab design to have a 16 bit bus

Why

Learnin'

  1. This is good prep for the last assignment, and shows how things can be added to the design
  2. Shows an alternative design style, and also a fun way to get bigger busses

Testing

👍

jameshughes89 and others added 2 commits March 24, 2025 13:00
Co-authored-by: Taras Mychaskiw <twentylemon@users.noreply.github.com>
@jameshughes89 jameshughes89 merged commit 40ba29f into main Mar 24, 2025
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@jameshughes89 jameshughes89 deleted the lab-add_mul-create branch March 24, 2025 16:03
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3 participants