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Pull requests: llvm/circt
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[HW][AIG] Add InstancePath CAPI and use native structures for AIG longest path analysis
#8760
opened Jul 22, 2025 by
uenoku
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[Comb] Add comb.reverse operation with Verilog Export
#8758
opened Jul 21, 2025 by
mafeguimaraes
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Add check for casting bundle with elements in different directions
#8750
opened Jul 21, 2025 by
unlsycn
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[Support] Add NPN class for Boolean function canonicalization
#8747
opened Jul 20, 2025 by
uenoku
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[FIRRTL] Make enums behave less like aggregates
FIRRTL
Involving the `firrtl` dialect
#8742
opened Jul 19, 2025 by
youngar
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[Seq] Add a pass to convert an array seq.firreg to seq.firmem
#8716
opened Jul 16, 2025 by
prithayan
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[FIRRTL][CreateSiFiveMetadata] Add memory read-under-write behavior to emitted metadata
#8604
opened Jun 26, 2025 by
fzi-hielscher
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[CMake] Allow Python discovery from virtual environment
#8520
opened May 30, 2025 by
hamidelmaazouz
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[SharedResourcesProblem] [Simplex Scheduler] Simplex scheduler deals with multiple resource constraints
#8480
opened May 13, 2025 by
jiahanxie353
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[SCFToCalyx] Modify top-level function in place and propagate external memory allocations
#8446
opened Apr 25, 2025 by
jiahanxie353
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[ImportVerilog] Convert the unpacked array to a simple bit vector
#8392
opened Apr 4, 2025 by
AnnuCode
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When replacing a register with its reset value, attempt width coercion
FIRRTL
Involving the `firrtl` dialect
#8379
opened Apr 1, 2025 by
rwy7
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Updated in the last three days: updated:>2025-07-19.