Attempt to fix Issue 87497

[Red-RobinHood]

No description provided.

[github-actions]

Thank you for submitting a Pull Request (PR) to the LLVM Project!

This PR will be automatically labeled and the relevant teams will be notified.

If you wish to, you can add reviewers by using the "Reviewers" section on this page.

If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using @ followed by their GitHub username.

If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers.

If you have further questions, they may be answered by the LLVM GitHub User Guide.

You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums.

[llvmbot]

@llvm/pr-subscribers-backend-aarch64

Author: None (Red-RobinHood)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/167177.diff

2 Files Affected:

• (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+32)
• (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.h (+7)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index c8a038fa99b30..7604cdc786268 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -31527,6 +31527,38 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
       Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth);
 }
 
+bool AArch64TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
+    SDValue Op,
+    const APInt &DemandedElts,
+    APInt &KnownUndef,
+    APInt &KnownZero,
+    TargetLoweringOpt &TLO,
+    unsigned Depth) const {
+
+  SDNode *N = Op.getNode();
+  unsigned Opc = N->getOpcode();
+
+  if (Opc != AArch64ISD::DUPLANE8 &&
+      Opc != AArch64ISD::DUPLANE16 &&
+      Opc != AArch64ISD::DUPLANE32 &&
+      Opc != AArch64ISD::DUPLANE64)
+    return false;
+
+  if (DemandedElts.popcount() != 1)
+  return false;
+
+  SDValue Src  = N->getOperand(0);
+  SDValue Lane = N->getOperand(1);
+
+  SDLoc DL(N);
+  SelectionDAG &DAG = TLO.DAG;
+
+  SDValue Extracted = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Src.getValueType().getScalarType(), Src, Lane);
+  SDValue Splat = DAG.getSplatVector(Op.getValueType(), DL, Extracted);
+
+  return TLO.CombineTo(Op, Splat);
+}
+
 bool AArch64TargetLowering::canCreateUndefOrPoisonForTargetNode(
     SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
     bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const {
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 70bfae717fb76..6cd26fe871a60 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -880,6 +880,13 @@ class AArch64TargetLowering : public TargetLowering {
                                          TargetLoweringOpt &TLO,
                                          unsigned Depth) const override;
 
+  bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op,
+                                          const APInt &DemandedElts,
+                                          APInt &KnownUndef,
+                                          APInt &KnownZero,
+                                          TargetLoweringOpt &TLO,
+                                          unsigned Depth) const override;
+
   bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
                                            const APInt &DemandedElts,
                                            const SelectionDAG &DAG,