Merge pull request #137 from os-fpga/fail_sim_1.6.0

Fail sim 1.6.0

Author: bilal458

sim_models/tb/FIFO18KX2_tb.v

@@ -14,11 +14,15 @@ module CLK_BUF (
 
    assign O = I ;
 
-   `ifndef SYNTHESIS
-      specify
-       (I => O) = (0, 0);
-      endspecify
-  `endif //  `ifndef SYNTHESIS
+   `ifndef SYNTHESIS  
+    `ifdef TIMED_SIM
+      specparam T1 = 0.5;
+       specify
+         (I => O) = (T1);
+       endspecify
+    
+    `endif // `ifdef TIMED_SIM  
+   `endif //  `ifndef SYNTHESIS
 
 
 

sim_models/verilog/CLK_BUF.v

@@ -34,7 +34,6 @@ module DLY_SEL_DECODER (
   output reg [2:0] DLY19_CNTRL // Output Bus
 );
 
-
 always @(*) 
 begin
   DLY0_CNTRL  = 3'b000;
@@ -85,5 +84,93 @@ begin
 end
 
 
+
+`ifndef SYNTHESIS  
+ `ifdef TIMED_SIM
+   specparam T1 = 0.4;
+
+    specify
+      if (DLY_ADDR == 5'd0)
+      (DLY_LOAD => DLY0_CNTRL)   = T1;
+      (DLY_ADJ => DLY0_CNTRL)    = T1;
+      (DLY_INCDEC => DLY0_CNTRL) = T1;
+      if (DLY_ADDR == 5'd1)
+      (DLY_LOAD => DLY1_CNTRL)   = T1;
+      (DLY_ADJ => DLY1_CNTRL)    = T1;
+      (DLY_INCDEC => DLY1_CNTRL) = T1;
+      if (DLY_ADDR == 5'd2)
+      (DLY_LOAD => DLY2_CNTRL)   = T1;
+      (DLY_ADJ => DLY2_CNTRL)    = T1;
+      (DLY_INCDEC => DLY2_CNTRL) = T1;
+      if (DLY_ADDR == 5'd3)
+      (DLY_LOAD => DLY3_CNTRL)   = T1;
+      (DLY_ADJ => DLY3_CNTRL)    = T1;
+      (DLY_INCDEC => DLY3_CNTRL) = T1;
+      if (DLY_ADDR == 5'd4)
+      (DLY_LOAD => DLY4_CNTRL)   = T1;
+      (DLY_ADJ => DLY4_CNTRL)    = T1;
+      (DLY_INCDEC => DLY4_CNTRL) = T1;
+      if (DLY_ADDR == 5'd5)
+      (DLY_LOAD => DLY5_CNTRL)   = T1;
+      (DLY_ADJ => DLY5_CNTRL)    = T1;
+      (DLY_INCDEC => DLY5_CNTRL) = T1;
+      if (DLY_ADDR == 5'd6)
+      (DLY_LOAD => DLY6_CNTRL)   = T1;
+      (DLY_ADJ => DLY6_CNTRL)    = T1;
+      (DLY_INCDEC => DLY6_CNTRL) = T1;
+      if (DLY_ADDR == 5'd7)
+      (DLY_LOAD => DLY7_CNTRL)   = T1;
+      (DLY_ADJ => DLY7_CNTRL)    = T1;
+      (DLY_INCDEC => DLY7_CNTRL) = T1;
+      if (DLY_ADDR == 5'd8)
+      (DLY_LOAD => DLY8_CNTRL)   = T1;
+      (DLY_ADJ => DLY8_CNTRL)    = T1;
+      (DLY_INCDEC => DLY8_CNTRL) = T1;
+      if (DLY_ADDR == 5'd9)
+      (DLY_LOAD => DLY9_CNTRL)   = T1;
+      (DLY_ADJ => DLY9_CNTRL)    = T1;
+      (DLY_INCDEC => DLY9_CNTRL) = T1;
+      if (DLY_ADDR == 5'd10)
+      (DLY_LOAD => DLY10_CNTRL)   = T1;
+      (DLY_ADJ => DLY10_CNTRL)    = T1;
+      (DLY_INCDEC => DLY10_CNTRL) = T1;
+      if (DLY_ADDR == 5'd12)
+      (DLY_LOAD => DLY12_CNTRL)   = T1;
+      (DLY_ADJ => DLY12_CNTRL)    = T1;
+      (DLY_INCDEC => DLY12_CNTRL) = T1;
+      if (DLY_ADDR == 5'd13)
+      (DLY_LOAD => DLY13_CNTRL)   = T1;
+      (DLY_ADJ => DLY13_CNTRL)    = T1;
+      (DLY_INCDEC => DLY13_CNTRL) = T1;
+      if (DLY_ADDR == 5'd14)
+      (DLY_LOAD => DLY14_CNTRL)   = T1;
+      (DLY_ADJ => DLY14_CNTRL)    = T1;
+      (DLY_INCDEC => DLY14_CNTRL) = T1;
+      if (DLY_ADDR == 5'd15)
+      (DLY_LOAD => DLY15_CNTRL)   = T1;
+      (DLY_ADJ => DLY15_CNTRL)    = T1;
+      (DLY_INCDEC => DLY15_CNTRL) = T1;
+      if (DLY_ADDR == 5'd16)
+      (DLY_LOAD => DLY16_CNTRL)   = T1;
+      (DLY_ADJ => DLY16_CNTRL)    = T1;
+      (DLY_INCDEC => DLY16_CNTRL) = T1;
+      if (DLY_ADDR == 5'd17)
+      (DLY_LOAD => DLY17_CNTRL)   = T1;
+      (DLY_ADJ => DLY17_CNTRL)    = T1;
+      (DLY_INCDEC => DLY17_CNTRL) = T1;
+      if (DLY_ADDR == 5'd18)
+      (DLY_LOAD => DLY18_CNTRL)   = T1;
+      (DLY_ADJ => DLY18_CNTRL)    = T1;
+      (DLY_INCDEC => DLY18_CNTRL) = T1;
+      if (DLY_ADDR == 5'd19)
+      (DLY_LOAD => DLY19_CNTRL)   = T1;
+      (DLY_ADJ => DLY19_CNTRL)    = T1;
+      (DLY_INCDEC => DLY19_CNTRL) = T1;
+
+    endspecify
+
+  `endif // `ifdef TIMED_SIM  
+`endif //  `ifndef SYNTHESIS
+
 endmodule
 `endcelldefine

sim_models/verilog/DLY_SEL_DECODER.v

@@ -14,12 +14,16 @@ module FCLK_BUF (
 
    assign O = I ;
 
-  `ifndef SYNTHESIS
+   `ifndef SYNTHESIS  
+    `ifdef TIMED_SIM
+    
+     specparam T1 = 0.3;
       specify
-       (I => O) = (0, 0);
+        (I => O) = T1;
       endspecify
-  `endif //  `ifndef SYNTHESIS
-   
-
+     
+    `endif // `ifdef TIMED_SIM  
+   `endif //  `ifndef SYNTHESIS
+ 
 endmodule
 `endcelldefine