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@rsetaluri rsetaluri requested a review from leonardt January 4, 2023 21:19
with push_block(curr.then_block):
sv.BPAssignOp(operands=[wire, data[index]])
with push_block(curr.else_block):
_process()
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Will the lack of else logic here be problematic for downstream tools? I could imagine a potential latch inference being triggered if the tool doesn't reason about all possible values being matched. In fact, if there is a non power of two number of inputs then there is a potential for a latch (e.g. if the select logic is generated incorrectly w.r.t. to the number of mux inputs, it's possible for the select value to be equal to a constant that's greater than len(data)). IIRC, MLIR would normally emit the mux as an array create/select. Perhaps in Verilog this is okay because the "extra" select values are ignored?

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@rsetaluri rsetaluri Jan 5, 2023

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Finalizing need with customer. Will report back what codegen is desired. For now can hold off on merging.

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2 participants