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added hierarchy test with custom env #486

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fc2fa43
added hierarchy test with custom env
rdaly525 Nov 8, 2019
e842318
added gold files
rdaly525 Nov 8, 2019
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89 changes: 89 additions & 0 deletions tests/test_syntax/gold/CustomEnvHier.json
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{"top":"global.TestBasic",
"namespaces":{
"global":{
"modules":{
"Register":{
"type":["Record",[
["I",["Array",2,"BitIn"]],
["CLK",["Named","coreir.clkIn"]],
["O",["Array",2,"Bit"]]
]],
"instances":{
"Register_comb_inst0":{
"modref":"global.Register_comb"
},
"reg_P_inst0":{
"genref":"coreir.reg",
"genargs":{"width":["Int",2]},
"modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",2],"2'h0"]}
}
},
"connections":[
["self.I","Register_comb_inst0.I"],
["reg_P_inst0.in","Register_comb_inst0.O0"],
["self.O","Register_comb_inst0.O1"],
["reg_P_inst0.out","Register_comb_inst0.self_value_O"],
["self.CLK","reg_P_inst0.clk"]
]
},
"Register_comb":{
"type":["Record",[
["I",["Array",2,"BitIn"]],
["self_value_O",["Array",2,"BitIn"]],
["O0",["Array",2,"Bit"]],
["O1",["Array",2,"Bit"]]
]],
"connections":[
["self.O0","self.I"],
["self.self_value_O","self.O1"]
]
},
"TestBasic":{
"type":["Record",[
["I",["Array",2,"BitIn"]],
["CLK",["Named","coreir.clkIn"]],
["O",["Array",2,"Bit"]]
]],
"instances":{
"Register_inst0":{
"modref":"global.Register"
},
"TestBasic_comb_inst0":{
"modref":"global.TestBasic_comb"
},
"reg_P_inst0":{
"genref":"coreir.reg",
"genargs":{"width":["Int",2]},
"modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",2],"2'h2"]}
}
},
"connections":[
["self.CLK","Register_inst0.CLK"],
["TestBasic_comb_inst0.O1","Register_inst0.I"],
["TestBasic_comb_inst0.self_y_O","Register_inst0.O"],
["self.I","TestBasic_comb_inst0.I"],
["reg_P_inst0.in","TestBasic_comb_inst0.O0"],
["self.O","TestBasic_comb_inst0.O2"],
["reg_P_inst0.out","TestBasic_comb_inst0.self_x_O"],
["self.CLK","reg_P_inst0.clk"]
]
},
"TestBasic_comb":{
"type":["Record",[
["I",["Array",2,"BitIn"]],
["self_x_O",["Array",2,"BitIn"]],
["self_y_O",["Array",2,"BitIn"]],
["O0",["Array",2,"Bit"]],
["O1",["Array",2,"Bit"]],
["O2",["Array",2,"Bit"]]
]],
"connections":[
["self.O0","self.I"],
["self.self_x_O","self.O1"],
["self.self_y_O","self.O2"]
]
}
}
}
}
}
42 changes: 42 additions & 0 deletions tests/test_syntax/gold/CustomEnvHier.v
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module coreir_reg #(parameter width = 1, parameter clk_posedge = 1, parameter init = 1) (input clk, input [width-1:0] in, output [width-1:0] out);
reg [width-1:0] outReg=init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= in;
end
assign out = outReg;
endmodule

module TestBasic_comb (input [1:0] I, output [1:0] O0, output [1:0] O1, output [1:0] O2, input [1:0] self_x_O, input [1:0] self_y_O);
assign O0 = I;
assign O1 = self_x_O;
assign O2 = self_y_O;
endmodule

module Register_comb (input [1:0] I, output [1:0] O0, output [1:0] O1, input [1:0] self_value_O);
assign O0 = I;
assign O1 = self_value_O;
endmodule

module Register (input CLK, input [1:0] I, output [1:0] O);
wire [1:0] Register_comb_inst0_O0;
wire [1:0] Register_comb_inst0_O1;
wire [1:0] reg_P_inst0_out;
Register_comb Register_comb_inst0(.I(I), .O0(Register_comb_inst0_O0), .O1(Register_comb_inst0_O1), .self_value_O(reg_P_inst0_out));
coreir_reg #(.clk_posedge(1), .init(2'h0), .width(2)) reg_P_inst0(.clk(CLK), .in(Register_comb_inst0_O0), .out(reg_P_inst0_out));
assign O = Register_comb_inst0_O1;
endmodule

module TestBasic (input CLK, input [1:0] I, output [1:0] O);
wire [1:0] Register_inst0_O;
wire [1:0] TestBasic_comb_inst0_O0;
wire [1:0] TestBasic_comb_inst0_O1;
wire [1:0] TestBasic_comb_inst0_O2;
wire [1:0] reg_P_inst0_out;
Register Register_inst0(.CLK(CLK), .I(TestBasic_comb_inst0_O1), .O(Register_inst0_O));
TestBasic_comb TestBasic_comb_inst0(.I(I), .O0(TestBasic_comb_inst0_O0), .O1(TestBasic_comb_inst0_O1), .O2(TestBasic_comb_inst0_O2), .self_x_O(reg_P_inst0_out), .self_y_O(Register_inst0_O));
coreir_reg #(.clk_posedge(1), .init(2'h2), .width(2)) reg_P_inst0(.clk(CLK), .in(TestBasic_comb_inst0_O0), .out(reg_P_inst0_out));
assign O = TestBasic_comb_inst0_O2;
endmodule

94 changes: 94 additions & 0 deletions tests/test_syntax/gold/CustomEnvHierARST.json
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{"top":"global.TestBasic",
"namespaces":{
"global":{
"modules":{
"Register":{
"type":["Record",[
["I",["Array",2,"BitIn"]],
["CLK",["Named","coreir.clkIn"]],
["ASYNCRESET",["Named","coreir.arstIn"]],
["O",["Array",2,"Bit"]]
]],
"instances":{
"Register_comb_inst0":{
"modref":"global.Register_comb"
},
"reg_PR_inst0":{
"genref":"coreir.reg_arst",
"genargs":{"width":["Int",2]},
"modargs":{"arst_posedge":["Bool",true], "clk_posedge":["Bool",true], "init":[["BitVector",2],"2'h0"]}
}
},
"connections":[
["self.I","Register_comb_inst0.I"],
["reg_PR_inst0.in","Register_comb_inst0.O0"],
["self.O","Register_comb_inst0.O1"],
["reg_PR_inst0.out","Register_comb_inst0.self_value_O"],
["self.ASYNCRESET","reg_PR_inst0.arst"],
["self.CLK","reg_PR_inst0.clk"]
]
},
"Register_comb":{
"type":["Record",[
["I",["Array",2,"BitIn"]],
["self_value_O",["Array",2,"BitIn"]],
["O0",["Array",2,"Bit"]],
["O1",["Array",2,"Bit"]]
]],
"connections":[
["self.O0","self.I"],
["self.self_value_O","self.O1"]
]
},
"TestBasic":{
"type":["Record",[
["I",["Array",2,"BitIn"]],
["CLK",["Named","coreir.clkIn"]],
["ASYNCRESET",["Named","coreir.arstIn"]],
["O",["Array",2,"Bit"]]
]],
"instances":{
"Register_inst0":{
"modref":"global.Register"
},
"TestBasic_comb_inst0":{
"modref":"global.TestBasic_comb"
},
"reg_PR_inst0":{
"genref":"coreir.reg_arst",
"genargs":{"width":["Int",2]},
"modargs":{"arst_posedge":["Bool",true], "clk_posedge":["Bool",true], "init":[["BitVector",2],"2'h2"]}
}
},
"connections":[
["self.ASYNCRESET","Register_inst0.ASYNCRESET"],
["self.CLK","Register_inst0.CLK"],
["TestBasic_comb_inst0.O1","Register_inst0.I"],
["TestBasic_comb_inst0.self_y_O","Register_inst0.O"],
["self.I","TestBasic_comb_inst0.I"],
["reg_PR_inst0.in","TestBasic_comb_inst0.O0"],
["self.O","TestBasic_comb_inst0.O2"],
["reg_PR_inst0.out","TestBasic_comb_inst0.self_x_O"],
["self.ASYNCRESET","reg_PR_inst0.arst"],
["self.CLK","reg_PR_inst0.clk"]
]
},
"TestBasic_comb":{
"type":["Record",[
["I",["Array",2,"BitIn"]],
["self_x_O",["Array",2,"BitIn"]],
["self_y_O",["Array",2,"BitIn"]],
["O0",["Array",2,"Bit"]],
["O1",["Array",2,"Bit"]],
["O2",["Array",2,"Bit"]]
]],
"connections":[
["self.O0","self.I"],
["self.self_x_O","self.O1"],
["self.self_y_O","self.O2"]
]
}
}
}
}
}
45 changes: 45 additions & 0 deletions tests/test_syntax/gold/CustomEnvHierARST.v
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module coreir_reg_arst #(parameter width = 1, parameter arst_posedge = 1, parameter clk_posedge = 1, parameter init = 1) (input clk, input arst, input [width-1:0] in, output [width-1:0] out);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk, posedge real_rst) begin
if (real_rst) outReg <= init;
else outReg <= in;
end
assign out = outReg;
endmodule

module TestBasic_comb (input [1:0] I, output [1:0] O0, output [1:0] O1, output [1:0] O2, input [1:0] self_x_O, input [1:0] self_y_O);
assign O0 = I;
assign O1 = self_x_O;
assign O2 = self_y_O;
endmodule

module Register_comb (input [1:0] I, output [1:0] O0, output [1:0] O1, input [1:0] self_value_O);
assign O0 = I;
assign O1 = self_value_O;
endmodule

module Register (input ASYNCRESET, input CLK, input [1:0] I, output [1:0] O);
wire [1:0] Register_comb_inst0_O0;
wire [1:0] Register_comb_inst0_O1;
wire [1:0] reg_PR_inst0_out;
Register_comb Register_comb_inst0(.I(I), .O0(Register_comb_inst0_O0), .O1(Register_comb_inst0_O1), .self_value_O(reg_PR_inst0_out));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(2'h0), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(Register_comb_inst0_O0), .out(reg_PR_inst0_out));
assign O = Register_comb_inst0_O1;
endmodule

module TestBasic (input ASYNCRESET, input CLK, input [1:0] I, output [1:0] O);
wire [1:0] Register_inst0_O;
wire [1:0] TestBasic_comb_inst0_O0;
wire [1:0] TestBasic_comb_inst0_O1;
wire [1:0] TestBasic_comb_inst0_O2;
wire [1:0] reg_PR_inst0_out;
Register Register_inst0(.ASYNCRESET(ASYNCRESET), .CLK(CLK), .I(TestBasic_comb_inst0_O1), .O(Register_inst0_O));
TestBasic_comb TestBasic_comb_inst0(.I(I), .O0(TestBasic_comb_inst0_O0), .O1(TestBasic_comb_inst0_O1), .O2(TestBasic_comb_inst0_O2), .self_x_O(reg_PR_inst0_out), .self_y_O(Register_inst0_O));
coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(2'h2), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O0), .out(reg_PR_inst0_out));
assign O = TestBasic_comb_inst0_O2;
endmodule

36 changes: 36 additions & 0 deletions tests/test_syntax/test_sequential.py
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Expand Up @@ -158,6 +158,42 @@ def __call__(self, I: m.Bits[2]) -> m.Bits[2]:
_TestBasic = m.circuit.sequential(TestBasic,env=env)
compile_and_check("CustomEnv", _TestBasic, target)

def test_custom_env_hierarchy(target, async_reset):

@m.cache_definition
def DefineCustomRegister(width, init=0):
@m.circuit.sequential(async_reset=async_reset)
class Register:
def __init__(self):
self.value: m.Bits[width] = m.bits(init, width)

def __call__(self, I: m.Bits[width]) -> m.Bits[width]:
O = self.value
self.value = I
return O

return Register

Reg2 = DefineCustomRegister(2)

_globals = globals()
_globals.update({'_custom_local_var_':2})
env = ast_tools.stack.SymbolTable(locals=locals(),globals=_globals)

class TestBasic:
def __init__(self):
self.x: m.Bits[2] = m.bits(_custom_local_var_, 2)
self.y: Reg2 = Reg2()

def __call__(self, I: m.Bits[2]) -> m.Bits[2]:
O = self.y
self.y = self.x
self.x = I
return O

_TestBasic = m.circuit.sequential(env=env,async_reset=async_reset)(TestBasic)
compile_and_check("CustomEnvHier" + ("ARST" if async_reset else ""), _TestBasic, target)

def test_seq_hierarchy(target, async_reset):
@m.cache_definition
def DefineCustomRegister(width, init=0):
Expand Down