refactor: update SystemVerilog generator for improved match handling and output file naming

Author: AliAlaa88

backends/generators/sverilog/sverilog_generator.py

@@ -14,9 +14,6 @@
 
 def format_instruction_name(name):
     """Format instruction name for SystemVerilog (uppercase with underscores)."""
-    # Handle compressed instructions
-    if name.startswith("c."):
-        name = "C_" + name[2:]
     # Replace dots with underscores and convert to uppercase
     return name.replace(".", "_").upper()
 
@@ -26,76 +23,78 @@ def format_csr_name(name):
     return "CSR_" + name.replace(".", "_").upper()
 
 
-def match_to_sverilog_bits(match_str, is_compressed=False):
+def match_to_sverilog_bits(match_str):
     """Convert a match string to SystemVerilog bit pattern."""
     if not match_str:
-        return "32'b" + "?" * 32
-    
-    # For compressed instructions (16-bit), we need to handle them differently
-    # The riscv-opcodes format puts the 16-bit pattern in the lower 16 bits
+        logging.error(f"Empty match string encountered.")
+        # return "32'b" + "?" * 32
+
+    # For compressed instructions (16-bit), we need to handle them differently.
+    # The 16-bit pattern is in the lower 16 bits,
     # with the upper 16 bits as wildcards
-    if is_compressed or len(match_str) == 16:
+    if len(match_str) == 16:
         # Pad with wildcards on the left for 16-bit instructions
         match_str = "?" * 16 + match_str
     elif len(match_str) < 32:
         # For other cases, pad on the right
-        match_str = match_str + "-" * (32 - len(match_str))
-    
+        logging.error(f"Match string length is {len(match_str)}, expected 32 or 16.")
+        # match_str = match_str + "-" * (32 - len(match_str))
+
     # Convert to SystemVerilog format (0, 1, or ?)
-    result = []
-    for bit in match_str:
-        if bit == "0":
-            result.append("0")
-        elif bit == "1":
-            result.append("1")
-        else:  # '-' or any other character
-            result.append("?")
-    
+    result = match_str.replace("-", "?")
+
     return "32'b" + "".join(result)
 
 
 def generate_sverilog(instructions, csrs, output_file):
     """Generate SystemVerilog package file."""
     with open(output_file, "w") as f:
         # Write header
-        f.write("\n/* Automatically generated by parse_opcodes */\n")
+        f.write("\n/* Automatically generated by UDB */\n")
         f.write("package riscv_instr;\n")
-        
+
         # Find the maximum name length for alignment
-        max_instr_len = max((len(format_instruction_name(name)) for name in instructions.keys()), default=0)
-        max_csr_len = max((len(format_csr_name(csrs[addr])) for addr in csrs.keys()), default=0)
+        max_instr_len = max(
+            (len(format_instruction_name(name)) for name in instructions.keys()),
+            default=0,
+        )
+        max_csr_len = max(
+            (len(format_csr_name(csrs[addr])) for addr in csrs.keys()), default=0
+        )
         max_len = max(max_instr_len, max_csr_len)
-        
+
         # Write instruction parameters
         for name in sorted(instructions.keys()):
             encoding = instructions[name]
             sv_name = format_instruction_name(name)
             # Pad the name for alignment
             padded_name = sv_name.ljust(max_len)
-            
+            # if not name.startswith("v"):
+            #     logging.info(f"Processing instruction: {name}")
+            #     logging.info(f"Formatted instruction: {sv_name}")
+            #     logging.info(f"Padded instruction: {padded_name}")
+
             # Get the match pattern
             if isinstance(encoding, dict) and "match" in encoding:
                 match = encoding["match"]
             else:
                 # If no match field, use all wildcards
-                match = "-" * 32
-            
-            # Check if this is a compressed instruction
-            is_compressed = name.startswith("c.")
-            sv_bits = match_to_sverilog_bits(match, is_compressed)
-            f.write(f"  localparam [31:0] {padded_name} = {sv_bits};\n")
-        
+                logging.warning(f"No match field for instruction {name}.")
+
+            sv_bits = match_to_sverilog_bits(match)
+            f.write(f"  localparam logic [31:0] {padded_name} = {sv_bits};\n")
+
         # Write CSR parameters
         # CSRs are returned as {address: name} by load_csrs
         for addr in sorted(csrs.keys()):
             csr_name = csrs[addr]
             sv_name = format_csr_name(csr_name)
             # Pad the name for alignment
             padded_name = sv_name.ljust(max_len)
-            
+
             # Format CSR address as 12-bit hex
             f.write(f"  localparam logic [11:0] {padded_name} = 12'h{addr:03x};\n")
-        
+
         # Write footer
         f.write("\nendpackage\n")
 
@@ -115,9 +114,9 @@ def parse_args():
         help="Directory containing CSR YAML files",
     )
     parser.add_argument(
-        "--output", 
-        default="inst.sverilog", 
-        help="Output SystemVerilog file name"
+        "--output",
+        default="riscv_decode_package.svh",
+        help="Output SystemVerilog file name",
     )
     parser.add_argument(
         "--extensions",
@@ -176,4 +175,4 @@ def main():
 
 
 if __name__ == "__main__":
-    main()
+    main()

backends/generators/tasks.rake

@@ -110,6 +110,6 @@ namespace :gen do
     csr_dir = cfg_arch.path / "csr"
 
     # Run the SystemVerilog generator script using the same Python environment
-    sh "#{$root}/.home/.venv/bin/python3 #{$root}/backends/generators/sverilog/sverilog_generator.py --inst-dir=#{inst_dir} --csr-dir=#{csr_dir} --output=#{output_dir}inst.sverilog"
+    sh "#{$root}/.home/.venv/bin/python3 #{$root}/backends/generators/sverilog/sverilog_generator.py --inst-dir=#{inst_dir} --csr-dir=#{csr_dir} --output=#{output_dir}riscv_decode_package.svh"
   end
 end