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feat: Added operation fields for Zicfiss instructions. #1009
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26ba9a1
feat: added operation fields for zicfiss instructions
sudo-apt-abdullah 4209a09
feat: updated the files as suggested
sudo-apt-abdullah 995c733
used an atomic swap operation for ssamoswap.w/d
sudo-apt-abdullah fa6b16e
Merge branch 'main' into issue_995
sudo-apt-abdullah 0b12808
Merge branch 'main' into issue_995
sudo-apt-abdullah 23b883d
added base 64 in ssamoswap.d.yaml file
sudo-apt-abdullah 3a0a827
added c.sspush and c.sspopchk yaml files
sudo-apt-abdullah 60f5de5
Merge branch 'main' into issue_995
sudo-apt-abdullah 2206d7b
renamed the files for CI to pass
sudo-apt-abdullah eb97e74
fixed the syntax error
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,45 @@ | ||
| # Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. | ||
| # SPDX-License-Identifier: BSD-3-Clause-Clear | ||
|
|
||
| # yaml-language-server: $schema=../../../../schemas/inst_schema.json | ||
|
|
||
| $schema: inst_schema.json# | ||
| kind: instruction | ||
| name: c.sspopchk.x5 | ||
| long_name: Pop from the Shadow Stack, 16 bit version of sspopchk | ||
| description: | | ||
| The c.sspopchk x5 expands to sspopchk x5, which is defined for an XLEN wide read from | ||
| the current top of the shadow stack followed by an increment of the ssp by XLEN/8. | ||
| definedBy: Zicfiss | ||
| assembly: c.sspopchk_x5 | ||
| encoding: | ||
| match: "0110001010000001" | ||
| variables: [] | ||
| access: | ||
| s: always | ||
| u: always | ||
| vs: always | ||
| vu: always | ||
| data_independent_timing: false | ||
| operation(): | | ||
| Bits<12> ssp_addr = 0x011; | ||
| Csr csr_handle = direct_csr_lookup(ssp_addr); | ||
|
|
||
| if (csr_handle.valid == false) { | ||
| unimplemented_csr($encoding); | ||
| } else if ((mode() < PrivilegeMode::M && CSR[menvcfg].SSE == 0) || | ||
| (mode() == PrivilegeMode::U && CSR[senvcfg].SSE == 0)) { | ||
| raise(ExceptionCode::IllegalInstruction, mode(), $encoding); | ||
| } else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].SSE == 0) || | ||
| (mode() == PrivilegeMode::VU && (CSR[henvcfg].SSE == 0 || CSR[senvcfg].SSE == 0))) { | ||
| raise(ExceptionCode::VirtualInstruction, mode(), $encoding); | ||
| } | ||
|
|
||
| if ((CSR[menvcfg].SSE == 1'b1) || (CSR[henvcfg].SSE == 1'b1) || (CSR[senvcfg].SSE == 1'b1)) { | ||
| Bits<XLEN> ssp = csr_sw_read(csr_handle); | ||
| XReg temp = read_memory<XLEN>(ssp, $encoding); | ||
| if (temp != X[5]) { | ||
| raise(ExceptionCode::SoftwareCheck, mode(), $encoding); | ||
| } | ||
| csr_sw_write(csr_handle, (ssp + (XLEN/8))); | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,43 @@ | ||
| # Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. | ||
| # SPDX-License-Identifier: BSD-3-Clause-Clear | ||
|
|
||
| # yaml-language-server: $schema=../../../../schemas/inst_schema.json | ||
|
|
||
| $schema: inst_schema.json# | ||
| kind: instruction | ||
| name: c.sspush.x1 | ||
| long_name: Push to the Shadow Stack from register x1, 16 bit version of sspush | ||
| description: | | ||
| The c.sspush x1 expands to sspush x1, which is defined for decrement of the ssp by XLEN/8 | ||
| followed by a store of the value in the link register x1 to memory at the new top of the | ||
| shadow stack. | ||
| definedBy: Zicfiss | ||
| assembly: c.sspush_x1 | ||
| encoding: | ||
| match: "0110000010000001" | ||
| variables: [] | ||
| access: | ||
| s: always | ||
| u: always | ||
| vs: always | ||
| vu: always | ||
| data_independent_timing: false | ||
| operation(): | | ||
| Bits<12> ssp_addr = 0x011; | ||
| Csr csr_handle = direct_csr_lookup(ssp_addr); | ||
|
|
||
| if (csr_handle.valid == false) { | ||
| unimplemented_csr($encoding); | ||
| } else if ((mode() < PrivilegeMode::M && CSR[menvcfg].SSE == 0) || | ||
| (mode() == PrivilegeMode::U && CSR[senvcfg].SSE == 0)) { | ||
| raise(ExceptionCode::IllegalInstruction, mode(), $encoding); | ||
| } else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].SSE == 0) || | ||
| (mode() == PrivilegeMode::VU && (CSR[henvcfg].SSE == 0 || CSR[senvcfg].SSE == 0))) { | ||
| raise(ExceptionCode::VirtualInstruction, mode(), $encoding); | ||
| } | ||
|
|
||
| if ((CSR[menvcfg].SSE == 1'b1) || (CSR[henvcfg].SSE == 1'b1) || (CSR[senvcfg].SSE == 1'b1)) { | ||
| Bits<XLEN> ssp = csr_sw_read(csr_handle) - (XLEN/8); | ||
| write_memory<XLEN>(ssp, X[1], $encoding); | ||
| csr_sw_write(csr_handle, ssp); | ||
| } |
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could you add:
to this file?
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Sure, I've added this in ssamoswap.d.yaml file. One more question, am I supposed to add new files for C.SSPOPCHK and C.SSPUSH under the Zicfiss extension?
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These are present as
sspopchk.x1.yamland similar, although they is not really correct. I have PR #872 that needs attention which fixes these, but I haven't finished getting it to pass CI yet. (And haven't had a chance to do so recently.) You can proceed as you already have.There was a problem hiding this comment.
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In that PR, I can see that you merged sspopchk.x1.yaml & sspopchk.x5.yaml into single file sspopchk.yaml and sspush.x1.yaml & sspush.x5.yaml into file sspush.yaml, but can't see 16 bit version of sspush and sspopchk. Do we need to create separate files for that or I'm missing something?
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Ah, I conflated the two. Yes, we do need C.SSPOPCHK and C.SSPUSH. Note that they're a little weird because their encoding overrides some C.MOP encodings.
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Ok, I'll give it some time to understand and then will try to write those files as well.