v0.1.119: Add signed and unsigned remainder operations for RISC-V semantics (#160)
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Implement rules for `REM` and `REMU` instructions in `riscv.md`,
detailing their behavior and special cases. Update syntax definitions in
`word.md` to include remainder operations, and provide comprehensive
handling for division by zero and overflow scenarios. Adjust test
integration to utilize the `rv32em` architecture for relevant tests.
Close https://github.com/runtimeverification/zkevm-harness/issues/80
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Co-authored-by: devops <devops@runtimeverification.com>
