mcux: C40 flash (S32K3x): add S32K344 array geometry header, IP Aliases and Cleanup #618
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sumitbatra-nxp
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@sumitbatra-nxp Please submit this change to the SDK team. I have provided you details on where to submit the PR via our chat channel. |
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Let us know once this is accepted by the SDK team and update this PR if needed. |
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Sure.. |
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@manuargue @mmahadevan108 .. I have corrected all the comments from the SDK team and ones made by Manuel here. |
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@mmahadevan108 .. All changes are complete and mcusdk PR is also marked as fixed |
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Awaiting approval from @manuargue before merging this. |
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Hi @sumitbatra-nxp, could you please help to update README to record the patch, for examples: https://github.com/zephyrproject-rtos/hal_nxp/pull/597/files#diff-d76b726c36140769d6ad0c555299f9442e47a435a0758efde38d56c2ca775313R243? Thanks a lot. |
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- fsl_c40_flash.c: Initialize `ret` in FLASH_Erase() to
`kStatus_FLASH_Success` to avoid potential use-before-set warnings on some
toolchains/static analyzers (no functional change).
- S32K344_features.h: Define C40 array geometry for S32K344 using unsigned
constants:
* FSL_FEATURE_FLASH_C40_BLOCK_SIZE_CODE (1 MiB)
* FSL_FEATURE_FLASH_C40_BLOCK_COUNT_CODE (4)
* FSL_FEATURE_FLASH_C40_BLOCK_SIZE_DATA (256 KiB)
Note: erase/program granularities are controller-level and handled by driver.
- S32K344_glue_mcux.h: Provide conditional aliases mapping FLASH↔IP_FLASH and
PFLASH↔IP_PFLASH to harmonize SDK naming and improve build portability.
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
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@ZhaoxiangJin .. I tried adding something as per my understanding in the mcux/README, but I am not sure if that is what was required. |
sumitbatra-nxp
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The information is ok, thanks. |
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@manuargue , please revisit this PR. |
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Title: mcux: C40 flash (S32K3x): run mutating ops from SRAM for XIP; add S32K344 array geometry header
Summary
This PR adds features header describing the C40 array geometry.
No behavior change on non-XIP builds.
flash_c40: add SoC features header
Introduces fsl_c40_flash_features.h with S32K344 C40 geometry (block sizes/counts).
Purely additive; intended for consumers (e.g., Zephyr internal-flash glue) that need compile-time array parameters.
Rationale
On Cortex-M XIP systems, flash program/erase/lock sequences must not execute from the same flash array they modify. Relocating these critical routines to SRAM is a standard mitigation that avoids bus contention and hard faults, especially under bootloader + application scenarios.
Compatibility
No public API changes.
Testing
Hardware: NXP S32K344 (MR-CANHUBK3).
Verified program/erase and sector protection operations via Zephyr flash_shell and MCUboot chain-load.
Confirmed stable execution with functions relocated to SRAM.
Follow-ups / Consumers
Zephyr driver glue for C40 uses this update; following Zephyr PR bumps west.yml to this HAL revision.
This PR is created to support Zephyr PR - zephyrproject-rtos/zephyr#97401
Signed-off-by: Sumit Batra sumit.batra@nxp.com