cn0577_adaq2387x: Add testbench #241

StancaPop · 2025-08-05T16:06:54Z

PR Description

Add testbench support for cn0577 & adaq2387x.

PR Type

Bug fix (change that fixes an issue)
New feature (change that adds new functionality)
New test (change that adds new test program and/or testbench)
Breaking change (has dependencies in other repositories/testbenches)
Documentation (change that adds or modifies documentation)

PR Checklist

I have followed the code style guidelines
I have performed a self-review of changes
I have ran all testbenches affected by this PR
I have commented my code, at least hard-to-understand parts
I have signed off all commits from this PR
I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
I have not introduced new Warnings/Errors on compilation/elaboration/simulation
I have set the verbosity level to none for the test program

StancaPop · 2025-08-06T12:57:18Z

To be tested with analogdevicesinc/hdl#1870

caosjr · 2025-09-04T13:24:49Z

testbenches/project/cn0577/tests/test_program.sv

+
+  sanity_test();
+
+  #100


maybe it is on my side, but it is showing a weird character before #100. The same happens for other delays throughout the source code.

Does it show something like this on your side as well? I'm using Visual Studio Code, and this is something that manifested only now. Seems to be a new feature of VS Code, as in Vivado's integrated IDE and GitHub it shows normally.
On a side-note on this is that regardless of the IDE behavior, a timescale must be added to the end of the delay, so that the simulation tool will always wait for the specified amount of time, irrelevant of the simulation's global timescale. For example: #100ns;

yes, it is showing the same character. I have never seem it in other projects.

Can you recheck if the character is still showing?

caosjr · 2025-09-04T13:41:52Z

testbenches/project/cn0577/tests/test_program.sv

+// --------------------------
+// Wrapper function for AXI read verif
+// --------------------------
+task axi_read_v(


isn't it supposed to remove axi_read_v, axi_read, and axi_write and use its API? I guess in this case it would be adc_api, right?

Yes, it is. The AXI_LTC2387 is like most of the other IPs that are modular using the Common and ADC and/or DAC register maps. The LTC seems to be created using the Common and the ADC, so 2 APIs for it.

Cleaned up - removed the axi rd/wr and used the APIs.

caosjr · 2025-09-04T14:19:58Z

testbenches/project/cn0577/tests/test_program.sv

+  output          db_p,
+  output reg      dco_p,
+  output reg      dco_n,
+  output          cnv);


I think cnv port should be input for the testbench, no? The documentation for the LTC2387 shows this port as an input .

Done. Thank you for noticing.

StancaPop · 2025-09-11T13:43:44Z

To be used with the HDL main branch.

IstvanZsSzekely · 2025-09-12T12:41:37Z

testbenches/project/cn0577/system_bd.tcl

+adi_project_files [list \
+    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+]


ad_iobuf.v is not used in the design, so it should be removed.

IstvanZsSzekely · 2025-09-12T12:43:57Z

testbenches/project/cn0577/system_tb.sv

+  parameter ID = 0;
+  parameter FPGA_TECHNOLOGY = 1;
+  parameter IO_DELAY_GROUP = "adc_if_delay_group";
+  parameter DELAY_REFCLK_FREQUENCY = 200;


Unused parameters.

IstvanZsSzekely · 2025-09-12T12:44:10Z

testbenches/project/cn0577/system_tb.sv

+  // axi interface
+
+  reg                     s_axi_aclk = 1'b0;
+  reg                     s_axi_aresetn = 1'b0;
+  reg                     s_axi_awvalid = 1'b0;
+  reg        [15:0]       s_axi_awaddr = 16'b0;
+  wire                    s_axi_awready;
+  reg                     s_axi_wvalid = 1'b0;
+  reg        [31:0]       s_axi_wdata = 32'b0;
+  reg        [ 3:0]       s_axi_wstrb = 4'b0;
+  wire                    s_axi_wready;
+  wire                    s_axi_bvalid;
+  wire       [ 1:0]       s_axi_bresp;
+  reg                     s_axi_bready = 1'b0;
+  reg                     s_axi_arvalid = 1'b0;
+  reg        [15:0]       s_axi_araddr = 1'b0;
+  wire                    s_axi_arready;
+  wire                    s_axi_rvalid;
+  wire       [ 1:0]       s_axi_rresp;
+  wire       [31:0]       s_axi_rdata;
+  reg                     s_axi_rready = 1'b0;
+  reg        [ 2:0]       s_axi_awprot = 3'b0;
+  reg        [ 2:0]       s_axi_arprot = 3'b0;


Unused interface.

IstvanZsSzekely · 2025-09-12T12:44:40Z

testbenches/project/cn0577/system_tb.sv

+  initial begin
+    s_axi_aresetn <= 1'b0;
+    repeat(10) @(posedge s_axi_aclk);
+    s_axi_aresetn <= 1'b1;
+  end


Unused code block.

IstvanZsSzekely · 2025-09-12T12:46:29Z

testbenches/project/cn0577/cn0577_environment.sv

The CN0577 environment doesn't do anything, so it can be removed. Please remove from other files and dependencies as well.

IstvanZsSzekely · 2025-09-12T12:47:15Z

testbenches/project/cn0577/tests/test_program.sv

+                  `TH.`DDR_AXI.inst.IF);
+  cn0577_dmac_api = new(


Add an empty line between the two.

IstvanZsSzekely · 2025-09-12T12:47:30Z

testbenches/project/cn0577/tests/test_program.sv

+
+  sanity_tests();
+
+  #100ns;


Can be removed.

Just the delay or the entire sanity tests section?

StancaPop · 2025-09-17T13:13:54Z

Converting the testbench to draft since the cn0577 HDL reference design will be updated here: analogdevicesinc/hdl#1919

This will cause the testbench to fail because of the following modification:

ADC_RES parameter has been removed; the cn0577 design will support only the LTC2387-18 variant

Solution:

This testbench can be renamed and repurposed for the adaq2387x family, that was separated from the cn0577 (both being built around axi_ltc2387) and supports both resolutions. The HDL project is still under development.

Signed-off-by: Stanca Pop <stanca.pop@analog.com>

StancaPop · 2025-09-22T13:10:52Z

Since the cn0577 & adaq2387x projects have been separated in HDL, repurposed this testbench to support both projects.
To be tested with: https://github.com/analogdevicesinc/hdl/tree/add_adaq2387x_s

StancaPop requested a review from a team as a code owner August 5, 2025 16:06

StancaPop added the new New testbench label Aug 5, 2025

StancaPop marked this pull request as draft August 5, 2025 16:08

StancaPop marked this pull request as ready for review August 6, 2025 12:57

StancaPop mentioned this pull request Aug 8, 2025

docs: Add cn0577 project-based documentation #242

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StancaPop force-pushed the add_cn0577_tb_s branch 2 times, most recently from 8138e90 to 8979778 Compare August 12, 2025 12:34

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StancaPop requested review from IstvanZsSzekely and caosjr September 11, 2025 13:43

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StancaPop marked this pull request as draft September 17, 2025 13:14

cn0577: Initial commit

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Signed-off-by: Stanca Pop <stanca.pop@analog.com>

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cn0577_adaq2387x: Update tb to work for cn0577 & adaq2387x

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Signed-off-by: Stanca Pop <stanca.pop@analog.com>

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StancaPop changed the title ~~cn0577: Add testbench~~ cn0577_adaq2387x: Add testbench Sep 22, 2025

cn0577_adaq2387x: Add testbench #241

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StancaPop commented Aug 5, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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StancaPop commented Sep 11, 2025

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StancaPop commented Sep 17, 2025

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StancaPop commented Aug 5, 2025 •

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