cn0577_adaq2387x: Add testbench

testbenches/project/cn0577/Makefile

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+####################################################################################
+####################################################################################
+## Copyright (C) 2025 Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# Makeincludes
+include ../../../scripts/make_tb_path.mk
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_dmac.mk
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_converter.mk
+
+# Remaining test-bench dependencies except test programs
+
+LIB_DEPS += axi_pwm_gen
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_ltc2387
+
+# default test programs
+# Format is: <test name>
+TP := $(notdir $(basename $(wildcard tests/*.sv)))
+
+# config files should have the following format
+#  cfg_<param1>_<param2>.tcl
+CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
+
+# List of tests and configuration combinations that has to be run
+# Format is:  <configuration>:<test name>
+TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(addprefix $(cfg):, $(TP)))
+
+include $(ADI_TB_DIR)/scripts/project-sim.mk
+
+# usage :
+#
+# run specific test on a specific configuration in gui mode
+# 	make CFG=cfg1 TST=test_program MODE=gui
+#
+# run all test from a configuration
+# 	make cfg1
+
+####################################################################################
+####################################################################################

testbenches/project/cn0577/README.md

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+Usage :
+
+Run all tests in batch mode:
+
+	make
+
+
+Run all tests in GUI mode:
+
+	make MODE=gui
+
+
+Run specific test on a specific configuration in gui mode:
+
+	make CFG=<name of cfg> TST=<name of test> MODE=gui
+
+
+Run all test from a configuration:
+
+	make <name of cfg>
+
+
+Where:
+
+ * <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
+ * <name of test> is a file from the tests directory without the tcl extension
+

testbenches/project/cn0577/cfgs/cfg_1lane_16b.tcl

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+global ad_project_params
+
+set ad_project_params(TWOLANES) 0
+set ad_project_params(ADC_RES) 16

testbenches/project/cn0577/cfgs/cfg_1lane_18b.tcl

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+global ad_project_params
+
+set ad_project_params(TWOLANES) 0
+set ad_project_params(ADC_RES) 18

testbenches/project/cn0577/cfgs/cfg_2lanes_16b.tcl

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+global ad_project_params
+
+set ad_project_params(TWOLANES) 1
+set ad_project_params(ADC_RES) 16

testbenches/project/cn0577/cfgs/cfg_2lanes_18b.tcl

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+global ad_project_params
+
+set ad_project_params(TWOLANES) 1
+set ad_project_params(ADC_RES) 18

testbenches/project/cn0577/system_bd.tcl

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+# ***************************************************************************
+# ***************************************************************************
+# Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+global ad_project_params
+
+# system level parameters
+set TWOLANES $ad_project_params(TWOLANES)
+set ADC_RES $ad_project_params(ADC_RES)
+
+adi_project_files [list \
+    "$ad_hdl_dir/library/common/ad_iobuf.v" \
+]
+
+#
+#  Block design under test
+#
+
+source $ad_hdl_dir/projects/cn0577/common/cn0577_bd.tcl
+
+set BA_AXI_LTC2387 0x44A00000
+set_property offset $BA_AXI_LTC2387 [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387}]
+adi_sim_add_define "AXI_LTC2387_BA=[format "%d" ${BA_AXI_LTC2387}]"
+
+set BA_DMA 0x44A30000
+set_property offset $BA_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387_dma}]
+adi_sim_add_define "AXI_LTC2387_DMA_BA=[format "%d" ${BA_DMA}]"
+
+set BA_PWM 0x44A60000
+set_property offset $BA_PWM [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_pwm_gen}]
+adi_sim_add_define "AXI_PWM_GEN_BA=[format "%d" ${BA_PWM}]"

testbenches/project/cn0577/system_project.tcl

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+source ../../../scripts/adi_sim.tcl
+
+if {$argc < 1} {
+  puts "Expecting at least one argument that specifies the test configuration"
+  exit 1
+} else {
+  set cfg_file [lindex $argv 0]
+}
+
+# Read common config file
+source "cfgs/${cfg_file}"
+
+# Set the project name
+set project_name [file rootname $cfg_file]
+
+# Set project params
+global ad_project_params
+
+set TWOLANES $ad_project_params(TWOLANES)
+set ADC_RES $ad_project_params(ADC_RES)
+
+# Set to use SmartConnect or AXI Interconnect
+set use_smartconnect 1
+
+# Create the project
+adi_sim_project_xilinx $project_name "xc7z007sclg400-1"
+
+source $ad_tb_dir/library/includes/sp_include_dmac.tcl
+source $ad_tb_dir/library/includes/sp_include_pwm_gen.tcl
+source $ad_tb_dir/library/includes/sp_include_converter.tcl
+
+# Add test files to the project
+adi_sim_project_files [list \
+  "cn0577_environment.sv" \
+  "tests/test_program.sv" \
+]
+
+#set a default test program
+adi_sim_add_define "TEST_PROGRAM=test_program"
+
+adi_sim_generate $project_name

testbenches/project/cn0577/system_tb.sv

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+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+`include "utils.svh"
+
+module system_tb();
+
+  parameter ID = 0;
+  parameter FPGA_TECHNOLOGY = 1;
+  parameter IO_DELAY_GROUP = "adc_if_delay_group";
+  parameter DELAY_REFCLK_FREQUENCY = 200;
+
+  // dco delay compared to the reference clk
+  localparam DCO_DELAY = 12;
+
+  // reg signals
+
+  reg                     ref_clk = 1'b0;
+  reg                     dco_init = 1'b0;
+  reg                     cnv_out = 1'b0;
+  reg                     clk_gate = 1'b0;
+  reg                     dco_p;
+  reg                     dco_n;
+  reg                     da_p = 1'b0;
+  reg                     da_n = 1'b0;
+  reg                     db_p = 1'b0;
+  reg                     db_n = 1'b0;
+
+  // dma interface
+
+  wire                    adc_valid;
+  wire  [`ADC_RES-1:0]    adc_data;
+  reg                     adc_dovf = 1'b0;
+
+  // axi interface
+
+  reg                     s_axi_aclk = 1'b0;
+  reg                     s_axi_aresetn = 1'b0;
+  reg                     s_axi_awvalid = 1'b0;
+  reg        [15:0]       s_axi_awaddr = 16'b0;
+  wire                    s_axi_awready;
+  reg                     s_axi_wvalid = 1'b0;
+  reg        [31:0]       s_axi_wdata = 32'b0;
+  reg        [ 3:0]       s_axi_wstrb = 4'b0;
+  wire                    s_axi_wready;
+  wire                    s_axi_bvalid;
+  wire       [ 1:0]       s_axi_bresp;
+  reg                     s_axi_bready = 1'b0;
+  reg                     s_axi_arvalid = 1'b0;
+  reg        [15:0]       s_axi_araddr = 1'b0;
+  wire                    s_axi_arready;
+  wire                    s_axi_rvalid;
+  wire       [ 1:0]       s_axi_rresp;
+  wire       [31:0]       s_axi_rdata;
+  reg                     s_axi_rready = 1'b0;
+  reg        [ 2:0]       s_axi_awprot = 3'b0;
+  reg        [ 2:0]       s_axi_arprot = 3'b0;
+
+  // local wires and registers
+
+  wire  cnv;
+  reg   dco = 1'b0;
+
+  integer cnv_count = 0;
+
+  // test bench variables
+
+  always #25 ref_clk = ~ref_clk;
+  //always #2.564 ref_clk = ~ref_clk;
+
+  // ---------------------------------------------------------------------------
+  // Creating a "gate" through which the data clock can run (and only then)
+  // ---------------------------------------------------------------------------
+  always @ (*) begin
+    if (clk_gate == 1'b1) begin
+      dco_init = ref_clk;
+    end else begin
+      dco_init = 1'b0;
+    end
+  end
+
+  initial begin
+    s_axi_aresetn <= 1'b0;
+    repeat(10) @(posedge s_axi_aclk);
+    s_axi_aresetn <= 1'b1;
+  end
+  // Data clocks generation
+  // ---------------------------------------------------------------------------
+
+  always @ (dco_init) begin
+    dco_p <= #DCO_DELAY  dco_init;
+    dco_n <= #DCO_DELAY  ~dco_init;
+  end
+
+    `TEST_PROGRAM test(
+       .ref_clk (ref_clk),
+       .clk_gate (clk_gate),
+       .dco_in (dco_init),
+       .da_p (da_p),
+       .da_n (da_n),
+       .db_p (db_p),
+       .db_n (db_n),
+       .cnv (cnv));
+
+     test_harness `TH (
+       .ref_clk (ref_clk),
+       .sampling_clk (sampling_clk),
+       .dco_p (dco_p),
+       .dco_n (dco_n),
+       .cnv (cnv),
+       .da_n (da_n),
+       .da_p (da_p),
+       .db_n (db_n),
+       .db_p (db_p),
+       .clk_gate (clk_gate));
+
+endmodule
+