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feat: Added operation fields for Zicfiss instructions. #1009

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26ba9a1
feat: added operation fields for zicfiss instructions
sudo-apt-abdullah Aug 21, 2025
4209a09
feat: updated the files as suggested
sudo-apt-abdullah Aug 22, 2025
995c733
used an atomic swap operation for ssamoswap.w/d
sudo-apt-abdullah Aug 25, 2025
fa6b16e
Merge branch 'main' into issue_995
sudo-apt-abdullah Aug 25, 2025
0b12808
Merge branch 'main' into issue_995
sudo-apt-abdullah Aug 26, 2025
23b883d
added base 64 in ssamoswap.d.yaml file
sudo-apt-abdullah Aug 26, 2025
3a0a827
added c.sspush and c.sspopchk yaml files
sudo-apt-abdullah Sep 1, 2025
60f5de5
Merge branch 'main' into issue_995
sudo-apt-abdullah Sep 1, 2025
2206d7b
renamed the files for CI to pass
sudo-apt-abdullah Sep 3, 2025
eb97e74
fixed the syntax error
sudo-apt-abdullah Sep 3, 2025
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20 changes: 18 additions & 2 deletions spec/std/isa/inst/Zicfiss/ssamoswap.d.yaml
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@ThinkOpenly ThinkOpenly Aug 25, 2025

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could you add:

base: 64

to this file?

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@sudo-apt-abdullah sudo-apt-abdullah Aug 26, 2025

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Sure, I've added this in ssamoswap.d.yaml file. One more question, am I supposed to add new files for C.SSPOPCHK and C.SSPUSH under the Zicfiss extension?

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@ThinkOpenly ThinkOpenly Aug 26, 2025

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These are present as sspopchk.x1.yaml and similar, although they is not really correct. I have PR #872 that needs attention which fixes these, but I haven't finished getting it to pass CI yet. (And haven't had a chance to do so recently.) You can proceed as you already have.

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@sudo-apt-abdullah sudo-apt-abdullah Aug 27, 2025

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In that PR, I can see that you merged sspopchk.x1.yaml & sspopchk.x5.yaml into single file sspopchk.yaml and sspush.x1.yaml & sspush.x5.yaml into file sspush.yaml, but can't see 16 bit version of sspush and sspopchk. Do we need to create separate files for that or I'm missing something?

You can proceed as you already have.
You mean I should pick the changes from there, right?

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@ThinkOpenly ThinkOpenly Aug 27, 2025

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Ah, I conflated the two. Yes, we do need C.SSPOPCHK and C.SSPUSH. Note that they're a little weird because their encoding overrides some C.MOP encodings.

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@sudo-apt-abdullah sudo-apt-abdullah Aug 28, 2025

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Ok, I'll give it some time to understand and then will try to write those files as well.

Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,11 @@
$schema: inst_schema.json#
kind: instruction
name: ssamoswap.d
long_name: No synopsis available
long_name: Atomic Swap Doubleword from a Shadow Stack Location
description: |
No description available.
The `ssamoswap.w` atomically loads a 64-bit data value from address of a shadow
stack location in xs1, puts the loaded value into register xd, and stores the
64-bit value held in xs2 to the original address in xs1.
definedBy: Zicfiss
assembly: xd, xs2, xs1
encoding:
Expand All @@ -31,3 +33,17 @@ access:
vu: always
data_independent_timing: false
operation(): |
if (!implemented?(ExtensionName::S)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
} else if ((mode() < PrivilegeMode::M && CSR[menvcfg].SSE == 0) ||
(mode() == PrivilegeMode::U && CSR[senvcfg].SSE == 0)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
} else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].SSE == 0) ||
(mode() == PrivilegeMode::VU && (CSR[henvcfg].SSE == 0 || CSR[senvcfg].SSE == 0))) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}

if ((CSR[menvcfg].SSE == 1'b1) || (CSR[henvcfg].SSE == 1'b1) || (CSR[senvcfg].SSE == 1'b1)) {
XReg addr_in_ssp = X[xs1];
X[xd] = amo<64>(addr_in_ssp, X[xs2], AmoOperation::Swap, aq, rl, $encoding);
}
20 changes: 18 additions & 2 deletions spec/std/isa/inst/Zicfiss/ssamoswap.w.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,11 @@
$schema: inst_schema.json#
kind: instruction
name: ssamoswap.w
long_name: No synopsis available
long_name: Atomic Swap Word from a Shadow Stack Location
description: |
No description available.
The `ssamoswap.w` atomically loads a 32-bit data value from address of a shadow
stack location in xs1, puts the loaded value into register xd, and stores the
32-bit value held in xs2 to the original address in xs1.
definedBy: Zicfiss
assembly: xd, xs2, xs1
encoding:
Expand All @@ -31,3 +33,17 @@ access:
vu: always
data_independent_timing: false
operation(): |
if (!implemented?(ExtensionName::S)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
} else if ((mode() < PrivilegeMode::M && CSR[menvcfg].SSE == 0) ||
(mode() == PrivilegeMode::U && CSR[senvcfg].SSE == 0)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
} else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].SSE == 0) ||
(mode() == PrivilegeMode::VU && (CSR[henvcfg].SSE == 0 || CSR[senvcfg].SSE == 0))) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}

if ((CSR[menvcfg].SSE == 1'b1) || (CSR[henvcfg].SSE == 1'b1) || (CSR[senvcfg].SSE == 1'b1)) {
XReg addr_in_ssp = X[xs1];
X[xd] = amo<32>(addr_in_ssp, X[xs2][31:0], AmoOperation::Swap, aq, rl, $encoding);
}
26 changes: 24 additions & 2 deletions spec/std/isa/inst/Zicfiss/sspopchk.x1.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,10 @@
$schema: inst_schema.json#
kind: instruction
name: sspopchk.x1
long_name: No synopsis available
long_name: Pop from the Shadow Stack
description: |
No description available.
A shadow stack pop operation is defined as an XLEN wide read from the current top
of the shadow stack followed by an increment of the ssp by XLEN/8.
definedBy: Zicfiss
assembly: sspopchk_x1
encoding:
Expand All @@ -21,3 +22,24 @@ access:
vu: always
data_independent_timing: false
operation(): |
Bits<12> ssp_addr = 0x011;
Csr csr_handle = direct_csr_lookup(ssp_addr);

if (csr_handle.valid == false) {
unimplemented_csr($encoding);
} else if ((mode() < PrivilegeMode::M && CSR[menvcfg].SSE == 0) ||
(mode() == PrivilegeMode::U && CSR[senvcfg].SSE == 0)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
} else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].SSE == 0) ||
(mode() == PrivilegeMode::VU && (CSR[henvcfg].SSE == 0 || CSR[senvcfg].SSE == 0))) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}

if ((CSR[menvcfg].SSE == 1'b1) || (CSR[henvcfg].SSE == 1'b1) || (CSR[senvcfg].SSE == 1'b1)) {
Bits<XLEN> ssp = csr_sw_read(csr_handle);
XReg temp = read_memory<XLEN>(ssp, $encoding);
if (temp != X[1]) {
raise(ExceptionCode::SoftwareCheck, mode(), $encoding);
} else {
csr_sw_write(csr_handle, (ssp + (XLEN/8)));
}
26 changes: 24 additions & 2 deletions spec/std/isa/inst/Zicfiss/sspopchk.x5.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,10 @@
$schema: inst_schema.json#
kind: instruction
name: sspopchk.x5
long_name: No synopsis available
long_name: Pop from the Shadow Stack
description: |
No description available.
A shadow stack pop operation is defined as an XLEN wide read from the current top
of the shadow stack followed by an increment of the ssp by XLEN/8.
definedBy: Zicfiss
assembly: sspopchk_x5
encoding:
Expand All @@ -21,3 +22,24 @@ access:
vu: always
data_independent_timing: false
operation(): |
Bits<12> ssp_addr = 0x011;
Csr csr_handle = direct_csr_lookup(ssp_addr);

if (csr_handle.valid == false) {
unimplemented_csr($encoding);
} else if ((mode() < PrivilegeMode::M && CSR[menvcfg].SSE == 0) ||
(mode() == PrivilegeMode::U && CSR[senvcfg].SSE == 0)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
} else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].SSE == 0) ||
(mode() == PrivilegeMode::VU && (CSR[henvcfg].SSE == 0 || CSR[senvcfg].SSE == 0))) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}

if ((CSR[menvcfg].SSE == 1'b1) || (CSR[henvcfg].SSE == 1'b1) || (CSR[senvcfg].SSE == 1'b1)) {
Bits<XLEN> ssp = csr_sw_read(csr_handle);
XReg temp = read_memory<XLEN>(ssp, $encoding);
if (temp != X[5]) {
raise(ExceptionCode::SoftwareCheck, mode(), $encoding);
} else {
csr_sw_write(csr_handle, (ssp + (XLEN/8)));
}
24 changes: 22 additions & 2 deletions spec/std/isa/inst/Zicfiss/sspush.x1.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,11 @@
$schema: inst_schema.json#
kind: instruction
name: sspush.x1
long_name: No synopsis available
long_name: Push to the Shadow Stack from register x1
description: |
No description available.
A shadow stack push operation is defined as decrement of the ssp by XLEN/8
followed by a store of the value in the link register x1 to memory at the
new top of the shadow stack.
definedBy: Zicfiss
assembly: sspush_x1
encoding:
Expand All @@ -21,3 +23,21 @@ access:
vu: always
data_independent_timing: false
operation(): |
Bits<12> ssp_addr = 0x011;
Csr csr_handle = direct_csr_lookup(ssp_addr);

if (csr_handle.valid == false) {
unimplemented_csr($encoding);
} else if ((mode() < PrivilegeMode::M && CSR[menvcfg].SSE == 0) ||
(mode() == PrivilegeMode::U && CSR[senvcfg].SSE == 0)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
} else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].SSE == 0) ||
(mode() == PrivilegeMode::VU && (CSR[henvcfg].SSE == 0 || CSR[senvcfg].SSE == 0))) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}

if ((CSR[menvcfg].SSE == 1'b1) || (CSR[henvcfg].SSE == 1'b1) || (CSR[senvcfg].SSE == 1'b1)) {
Bits<XLEN> ssp = csr_sw_read(csr_handle) - (XLEN/8);
write_memory<XLEN>(ssp, X[1], $encoding);
csr_sw_write(csr_handle, ssp);
}
24 changes: 22 additions & 2 deletions spec/std/isa/inst/Zicfiss/sspush.x5.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,11 @@
$schema: inst_schema.json#
kind: instruction
name: sspush.x5
long_name: No synopsis available
long_name: Push to the Shadow Stack from register x5
description: |
No description available.
A shadow stack push operation is defined as decrement of the ssp by XLEN/8
followed by a store of the value in the link register x5 to memory at the
new top of the shadow stack.
definedBy: Zicfiss
assembly: sspush_x5
encoding:
Expand All @@ -21,3 +23,21 @@ access:
vu: always
data_independent_timing: false
operation(): |
Bits<12> ssp_addr = 0x011;
Csr csr_handle = direct_csr_lookup(ssp_addr);

if (csr_handle.valid == false) {
unimplemented_csr($encoding);
} else if ((mode() < PrivilegeMode::M && CSR[menvcfg].SSE == 0) ||
(mode() == PrivilegeMode::U && CSR[senvcfg].SSE == 0)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
} else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].SSE == 0) ||
(mode() == PrivilegeMode::VU && (CSR[henvcfg].SSE == 0 || CSR[senvcfg].SSE == 0))) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}

if ((CSR[menvcfg].SSE == 1'b1) || (CSR[henvcfg].SSE == 1'b1) || (CSR[senvcfg].SSE == 1'b1)) {
Bits<XLEN> ssp = csr_sw_read(csr_handle) - (XLEN/8);
write_memory<XLEN>(ssp, X[5], $encoding);
csr_sw_write(csr_handle, ssp);
}
20 changes: 19 additions & 1 deletion spec/std/isa/inst/Zicfiss/ssrdp.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ kind: instruction
name: ssrdp
long_name: Read ssp into a Register
description: |
No description available.
Move the contents of ssp to a destination register.
definedBy: Zicfiss
assembly: xd
encoding:
Expand All @@ -24,3 +24,21 @@ access:
vu: always
data_independent_timing: false
operation(): |
Bits<12> ssp_addr = 0x011;
Csr csr_handle = direct_csr_lookup(ssp_addr);

if (csr_handle.valid == false) {
unimplemented_csr($encoding);
} else if ((mode() < PrivilegeMode::M && CSR[menvcfg].SSE == 0) ||
(mode() == PrivilegeMode::U && CSR[senvcfg].SSE == 0)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
} else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].SSE == 0) ||
(mode() == PrivilegeMode::VU && (CSR[henvcfg].SSE == 0 || CSR[senvcfg].SSE == 0))) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}

if ((CSR[menvcfg].SSE == 1'b1) || (CSR[henvcfg].SSE == 1'b1) || (CSR[senvcfg].SSE == 1'b1)) {
X[xd] = csr_sw_read(csr_handle);
} else {
X[xd] = 0;
}