arch: riscv: introduce common layer for RISC-V custom CSRs #93697
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| config CPU_HAS_ANDES_EXECIT | ||
| bool | ||
| help | ||
| The AndesCore supports EXEC.IT instruction. |
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help text indent is 1x tab followed by 2x spaces
| The AndesCore supports EXEC.IT instruction. | ||
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| config RISCV_CUSTOM_CSR_ANDES_EXECIT | ||
| bool "Andes V5 EXEC.IT extension" |
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why do any of these have prompts?
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This remains the original design from andestech/ae350 and telink/tlsr/tlsr951x.
The SoC selects Andes extensions through CPU_HAS_ANDES_XXX, while applications can decide whether to use them or not.
For example, a SoC may support the Andes HWDSP or PFT extension, but if the application doesn’t use them, the user can disable these features via these options.
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Removed old Kconfig option in adp_xc7k_ae350_clic_defconfig. Hi @kevinwang821020 , there are some issues with the dma_andes_atcdmac300 driver check or the adp_xc7k_ae350.conf in tests/drivers/dma. |
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I wonder if Either this is vendor specific in which case this should be in |
Based on the current atcdmac driver codebase, it need to do the cache operations(CONFIG_CACHE_MANAGEMENT) for chain_block when DCACHE is enabled, even CONFIG_NOCACHE_MEMORY is enable. I have already prepared a previous PR ( PR #85272 ) which includes fixing this problem. |
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Right, custom CSR is RISC-V feature, I think placing these in Moved the custom CSR common code to |
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RISC-V allows custom CSR implementation. Some SoCs from different vendors may share the same core or the same custom CSR definitions and drivers. This patch introduces 'arch/riscv/custom', which centralizes support for custom CSRs, allowing code reuse across SoCs that come from different vendors. Currently supported thess custom CSR: 1. Andes 2. Nuclei 3. OpenHWGroup CVA6 4. OpenISA RI5CY 5. OpenISA Zero-riscy Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Rework Andes-specific CSR to use RISC-V custom CSR common code. Move these stuff to 'arch/riscv/custom/andes': 1. Rename 'soc_v5.h' to 'andes_csr.h' for CSR definitions. 2. Replace '_start' with '__reset' hook for low-level CSR initialization. 3. Move CSR context to common macro '__custom_csr_save/restore_context'. 4. Move 'EXECIT' CSR support to common code. 5. Move PMA CSR driver to common code. 6. Use RISC-V common linker.ld instead of SoC-specific linker.ld. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
TLSR951x also supports Andes extended CSR. Reworks the following CSR handling to use the RISC-V custom CSR common code: 1. Use common macros for HWDSP CSR context save/restore. 2. Use common macros for PFT CSR context save/restore. 3. Use common low-level CSR initialization via __reset hook. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
GD32VF103 uses Nuclei-specific CSR. Move 'nuclei_csr.h' to 'arch/riscv/custom' to allow reuse across SoCs with the same Nuclei core. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
CVA6 supports custom CSR. Move 'cva6.h' to 'arch/riscv/custom/cva6_csr.h', allowing other SoCs using the CVA6 core to reuse the same CSR definitions. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Update OpenISA RI5CY and Zero-RISCY CSR handling to use RISC-V custom CSR common code. Move these stuff to 'arch/riscv/custom/openisa': 1. Rename 'soc_ri5cy.h' to 'ri5cy_csr.h' for CSR definitions. 2. Rename 'soc_zero_riscy.h' to 'zero_riscy_csr.h' for CSR definitions. 3. Move CSR context to common macro '__custom_csr_save/restore_context'. 4. Move compiler option '-march=rv32imcxpulpv2' to common code. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
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Rebased to pass CI. |
This PR is inspired by #91940.
RISC-V allows custom CSR implementation. Some SoCs from different SoC vendors may share the same core or the same custom CSR definitions and drivers.
For example, Andes AE350, Telink TLSR9518, and Egis ET171 all support Andes-specific CSRs.
This PR introduces
soc/common/riscv-customzephyr/arch/riscv/custom, which centralizes support for custom CSRs, allowing code reuse across SoCs that come from different vendors.Currently supported these custom CSR: