arch: riscv: introduce common layer for RISC-V custom CSRs

arch/riscv/CMakeLists.txt

@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 add_subdirectory(core)
+add_subdirectory_ifdef(CONFIG_RISCV_CUSTOM_CSR custom)
 
 zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/arch/riscv/error.h)
 

arch/riscv/Kconfig

@@ -121,6 +121,11 @@ config RISCV_PRIVILEGED
 	help
 	  Option selected by SoCs implementing the RISC-V privileged ISA.
 
+config RISCV_CUSTOM_CSR
+	bool
+	help
+	  Option selected by SoCs implementing the custom CSR.
+
 config RISCV_SOC_HAS_ISR_STACKING
 	bool
 	depends on !USERSPACE
@@ -527,4 +532,10 @@ config RISCV_NO_MTVAL_ON_FP_TRAP
 
 rsource "Kconfig.isa"
 
+if RISCV_CUSTOM_CSR
+
+rsource "custom/Kconfig"
+
+endif # RISCV_CUSTOM_CSR
+
 endmenu

arch/riscv/custom/CMakeLists.txt

@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Andes Technology Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES andes)
+add_subdirectory_ifdef(CONFIG_RISCV_CUSTOM_CSR_CVA6 openhwgroup/cva6)
+add_subdirectory_ifdef(CONFIG_RISCV_CUSTOM_CSR_NUCLEI nuclei)
+add_subdirectory_ifdef(CONFIG_RISCV_CUSTOM_CSR_RI5CY openisa/ri5cy)
+add_subdirectory_ifdef(CONFIG_RISCV_CUSTOM_CSR_ZERO_RISCY openisa/zero_riscy)

arch/riscv/custom/Kconfig

@@ -0,0 +1,40 @@
+# Copyright (c) 2025 Andes Technology Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Configuration options for RISC-V cores with custom CSR support
+
+config RISCV_CUSTOM_CSR_ANDES
+	bool
+	depends on DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED
+	help
+	  The RISC-V core supports Andes-specific custom CSRs.
+
+config RISCV_CUSTOM_CSR_CVA6
+	bool
+	depends on DT_HAS_OPENHWGROUP_CVA6_ENABLED
+	help
+	  The RISC-V core supports CVA6-specific custom CSRs.
+
+config RISCV_CUSTOM_CSR_NUCLEI
+	bool
+	depends on DT_HAS_NUCLEI_BUMBLEBEE_ENABLED
+	help
+	  The RISC-V core supports Nuclei-specific custom CSRs.
+
+config RISCV_CUSTOM_CSR_RI5CY
+	bool
+	depends on DT_HAS_OPENISA_RI5CY_ENABLED
+	help
+	  The RISC-V core supports RI5CY-specific custom CSRs.
+
+config RISCV_CUSTOM_CSR_ZERO_RISCY
+	bool
+	depends on DT_HAS_OPENISA_ZERO_RI5CY_ENABLED
+	help
+	  The RISC-V core supports Zero-Riscy-specific custom CSRs.
+
+if RISCV_CUSTOM_CSR_ANDES
+
+rsource "andes/Kconfig"
+
+endif # RISCV_CUSTOM_CSR_ANDES

arch/riscv/custom/andes/CMakeLists.txt

@@ -0,0 +1,21 @@
+# Copyright (c) 2025 Andes Technology Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA pma.c)
+zephyr_sources_ifndef(CONFIG_INCLUDE_RESET_VECTOR reset.S)
+zephyr_linker_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES_EXECIT RODATA SORT_KEY 0x0 execit.ld)
+zephyr_linker_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA RAM_SECTIONS SORT_KEY 0x0 pma_align_start.ld)
+zephyr_linker_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA RAM_SECTIONS SORT_KEY 0x0 pma_align_end.ld)
+
+# Note: AndeStar V5 DSP needs custom Andes V5 toolchain
+if(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP)
+  zephyr_cc_option(-mext-dsp)
+endif()
+
+# Note: AndeStar V5 EXEC.IT needs custom Andes V5 toolchain
+if(CONFIG_RISCV_CUSTOM_CSR_ANDES_EXECIT)
+  zephyr_cc_option(-mexecit)
+  zephyr_ld_options(-Wl,--mexecit)
+endif()

arch/riscv/custom/andes/Kconfig

@@ -0,0 +1,66 @@
+# Copyright (c) 2025 Andes Technology Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config CPU_HAS_ANDES_EXECIT
+	bool
+	help
+	  The AndesCore supports EXEC.IT instruction.
+
+config RISCV_CUSTOM_CSR_ANDES_EXECIT
+	bool "Andes V5 EXEC.IT extension"
+	depends on CPU_HAS_ANDES_EXECIT
+	depends on RISCV_ISA_EXT_C
+	depends on !RISCV_GENERIC_TOOLCHAIN
+	depends on !LINKER_USE_NO_RELAX
+	help
+	  The EXEC.IT extension (Execution on Instruction Table) generate
+	  a look-up table and replaces suitable 32-bit instructions with
+	  the 16-bit "exec.it <INDEX>".
+
+config CPU_HAS_ANDES_HWDSP
+	bool
+	help
+	  The AndesCore supports hardware DSP extension.
+
+config RISCV_CUSTOM_CSR_ANDES_HWDSP
+	bool "AndeStar V5 DSP ISA"
+	depends on CPU_HAS_ANDES_HWDSP
+	depends on !RISCV_GENERIC_TOOLCHAIN
+	help
+	  This option enables the AndeStar v5 hardware DSP, in order to
+	  support using the DSP instructions.
+
+config CPU_HAS_ANDES_PFT
+	bool
+	help
+	  The AndesCore supports PowerBrake extension.
+
+config RISCV_CUSTOM_CSR_ANDES_PFT
+	bool "Andes V5 PowerBrake extension"
+	depends on CPU_HAS_ANDES_PFT
+	help
+	  The PowerBrake extension throttles performance by reducing instruction
+	  executing rate.
+
+config CPU_HAS_ANDES_PMA
+	bool
+	help
+	  The AndesCore supports Programmable PMA.
+
+config RISCV_CUSTOM_CSR_ANDES_PMA
+	bool "Andes V5 Physical Memory Attribute (PMA)"
+	depends on CPU_HAS_ANDES_PMA
+	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
+	help
+	  This option enables the Andes V5 PMA, in order to support SW to
+	  configure physical memory attribute by PMA CSRs. The address
+	  matching of Andes V5 PMA is like RISC-V PMP NAPOT mode
+	  (power-of-two alignment).
+
+config RISCV_CUSTOM_CSR_ANDES_PMA_NAPOT_GRANULARITY
+	int
+	depends on RISCV_CUSTOM_CSR_ANDES_PMA
+	default 4096
+	help
+	  Minimum size (and alignment) of an PMA region. Use this symbol
+	  to guarantee minimum size and alignment of PMA regions.

soc/andestech/ae350/soc_v5.h → arch/riscv/custom/andes/andes_csr.h

@@ -1,11 +1,14 @@
 /*
- * Copyright (c) 2021 Andes Technology Corporation
- *
+ * Copyright (c) 2025 Andes Technology Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef __RISCV_ANDES_V5_SOC_V5_H_
-#define __RISCV_ANDES_V5_SOC_V5_H_
+#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_H_
+#define ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 /* Control and Status Registers (CSRs) available for Andes V5 SoCs */
 #define NDS_MMISC_CTL                0x7D0
@@ -46,4 +49,8 @@
 #define NDS_PMAADDR14                0xBDE
 #define NDS_PMAADDR15                0xBDF
 
-#endif /* __RISCV_ANDES_V5_SOC_V5_H_ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_H_ */

arch/riscv/custom/andes/csr_context.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2025 Andes Technology Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Extra definitions required for CONFIG_RISCV_SOC_CONTEXT_SAVE.
+ */
+
+#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_CONTEXT_H_
+#define ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_CONTEXT_H_
+
+#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
+
+/* Andes V5 specific registers. */
+#if defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT) && \
+	defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP)
+	#define CUSTOM_CSR_ESF_MEMBERS			\
+		uint32_t mxstatus;			\
+		uint32_t ucode				\
+
+	#define CUSTOM_CSR_ESF_INIT			\
+		0,					\
+		0
+
+#elif defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT)
+	#define CUSTOM_CSR_ESF_MEMBERS			\
+		uint32_t mxstatus
+
+	#define CUSTOM_CSR__ESF_INIT			\
+		0
+
+#elif defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP)
+	#define CUSTOM_CSR_ESF_MEMBERS			\
+		uint32_t ucode
+
+	#define CUSTOM_CSR_ESF_INIT			\
+		0
+
+#endif
+
+#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
+
+#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_CONTEXT_H_ */

arch/riscv/custom/andes/csr_irq.inc

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2025 Andes Technology Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/offsets.h>
+#include <zephyr/toolchain.h>
+#include <andes_csr.h>
+
+#ifdef CONFIG_64BIT
+	/* register-wide load/store based on ld/sd (XLEN = 64) */
+
+	.macro lr, rd, mem
+	ld \rd, \mem
+	.endm
+
+	.macro sr, rs, mem
+	sd \rs, \mem
+	.endm
+
+#else
+	/* register-wide load/store based on lw/sw (XLEN = 32) */
+
+	.macro lr, rd, mem
+	lw \rd, \mem
+	.endm
+
+	.macro sr, rs, mem
+	sw \rs, \mem
+	.endm
+
+#endif
+
+#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
+
+	.macro __custom_csr_save_context __soc_esf_reg reg
+
+#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT
+	csrr \reg, NDS_MXSTATUS
+	sr \reg, __soc_esf_t_mxstatus_OFFSET(\__soc_esf_reg)
+#endif
+
+#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP
+	csrr \reg, NDS_UCODE
+	sr \reg, __soc_esf_t_ucode_OFFSET(\__soc_esf_reg)
+#endif
+
+	.endm
+
+	.macro  __custom_csr_restore_context __soc_esf_reg reg
+
+#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT
+	lr \reg, __soc_esf_t_mxstatus_OFFSET(\__soc_esf_reg)
+	csrw NDS_MXSTATUS, \reg
+#endif
+#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP
+	lr \reg, __soc_esf_t_ucode_OFFSET(\__soc_esf_reg)
+	csrw NDS_UCODE, \reg
+#endif
+
+	.endm
+
+#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */

arch/riscv/custom/andes/csr_offsets.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Andes Technology Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Extra definitions required for CONFIG_RISCV_SOC_OFFSETS.
+ */
+
+#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_OFFSETS_H_
+#define ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_OFFSETS_H_
+
+#ifdef CONFIG_RISCV_SOC_OFFSETS
+
+/* Andes V5 specific registers. */
+#if defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT) && \
+	defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP)
+	#define GEN_CUSTOM_CSR_OFFSET_SYMS()		\
+		GEN_OFFSET_SYM(soc_esf_t, mxstatus);	\
+		GEN_OFFSET_SYM(soc_esf_t, ucode)
+
+#elif defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT)
+	#define GEN_CUSTOM_CSR_OFFSET_SYMS()		\
+		GEN_OFFSET_SYM(soc_esf_t, mxstatus)
+
+#elif defined(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP)
+	#define GEN_CUSTOM_CSR_OFFSET_SYMS()		\
+		GEN_OFFSET_SYM(soc_esf_t, ucode)
+
+#endif
+
+#endif /* CONFIG_RISCV_SOC_OFFSETS */
+
+#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_ANDES_CSR_OFFSETS_H_ */

soc/andestech/ae350/common_linker/execit.ld → arch/riscv/custom/andes/execit.ld

@@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2023 Andes Technology Corporation
- *
+ * Copyright (c) 2025 Andes Technology Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 

soc/andestech/ae350/pma.c → arch/riscv/custom/andes/pma.c

@@ -1,16 +1,14 @@
 /*
- * Copyright (c) 2021 Andes Technology Corporation
- *
+ * Copyright (c) 2025 Andes Technology Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc_v5.h"
-
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/linker/linker-defs.h>
 #include <zephyr/arch/riscv/csr.h>
+#include <andes_csr.h>
 
 #ifndef CONFIG_ASSERT
 #define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL
@@ -149,7 +147,7 @@ static void region_init(const uint32_t index,
 static int pma_region_is_valid(const struct pma_region *region)
 {
 	/* Region size must greater or equal to the minimum PMA region size */
-	if (region->size < CONFIG_SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE) {
+	if (region->size < CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA_NAPOT_GRANULARITY) {
 		return -EINVAL;
 	}
 
@@ -204,10 +202,10 @@ void pma_init(void)
 		/* This CPU doesn't support PMA */
 
 		__ASSERT(0, "CPU doesn't support PMA. "
-			    "Please disable CONFIG_SOC_ANDES_V5_PMA\n");
+			"Please disable CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA\n");
 #ifndef CONFIG_ASSERT
 		LOG_ERR("CPU doesn't support PMA. "
-			"Please disable CONFIG_SOC_ANDES_V5_PMA");
+			"Please disable CONFIG_RISCV_CUSTOM_CSR_ANDES_PMA");
 #endif
 		return;
 	}