My very own CPU architecture! Emulator availible!
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Updated
Jun 11, 2025 - C++
My very own CPU architecture! Emulator availible!
An FPGA-based single-cycle RISC-V processor (RV32I) implemented in SystemVerilog. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. This project is ideal for learning computer architecture, digital design, and RISC-V ISA implementation.
Sample Verilog codes for digital circuits
This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.
Digital Design and Computer Organisation Mini-project
A Repo that contains the source code for Digital Design and Computer Organisation course.
This project is my design of a basic ALU that can perform addition, subtraction, and bitwise logic operations. This project was designed in Logisim Evolution and implemented with TTL logic chips on breadboards.
My implementation of RISC-V CPU Core using TL-Verilog
🖥️ Digital Design and Computer Architecture
My solutions to Bilkent University Digital Design Course which focuses on SystemVerilog and computer architecture.
A collection of Verilog implementations and exercises covering fundamental digital design concepts that I have worked on.
PESU Sem 3: Mini project for Digital Design and Computer Organization
by M. Morris Mano, Michael D. Ciletti. 5th Edition
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