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rv32i-processor

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Awais-Asghar / Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

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An FPGA-based single-cycle RISC-V processor (RV32I) implemented in SystemVerilog. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. This project is ideal for learning computer architecture, digital design, and RISC-V ISA implementation.

fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor
  • Updated Jul 21, 2025
  • SystemVerilog

muhammadtalhasami / RV32I_Single_Cycle

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This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

vhdl verilog hardware-designs gtkwave pipeline-processor system-verilog rv32i verilator verilog-codes risc-v-assembly single-cycle-processor muhammadtalhasami-github- rv32i-processor fetch-stage-pipeline risc-v-processor risc-v-pipeline verilog-code-examples system-verilog-codes risc-v-processor-images single-cycle-processor-gtkwave-image
  • Updated Aug 10, 2024
  • Verilog

HafizMutahirAhmed / RV32I-5-Stage-Processor

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A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.

processor-architecture fpga processor riscv rtl vivado systemverilog hdl risc-v rv32i verilator processor-design fpga-programming arty-a7 risc-v-architecture five-stage riscof pipelined-processor rv32i-processor
  • Updated Jul 27, 2025
  • SystemVerilog

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